The present invention relates to a semiconductor device, and particularly to a process for producing a stacked capacitor of a DRAM cell.
The semiconductor memory device tends to be highly integrated with large capacity. Particularly, since the memory capacity of a DRAM cell including a transistor and a capacitor is determined by the volume of the capacitor, as the size of the cells gets smaller and smaller, it is necessary to ensure larger and larger volume of the capacitor. A typical example of DRAM cell capacitors with a large capacity is a stacked structure, wherein the storage electrodes are stacked on the substrate, so that the expanded surface areas of the storage electrodes are used to increase the capacity of the capacitor.
Referring to FIG. 1 for illustrating the cross section of a conventionally improved stacked capacitor, on the substrate 1 having element isolating oxide layer 2, source and drain regions 3 and 4, word line and bit line 5 and 10, and insulating layer 6 is there formed a capacitor including fin-shaped storage electrode 7 contacting the source region 3, dielectric layer 8 and plate electrode 9. Over the whole surface of the substrate 1 is laid element protecting layer 11. The fin-shaped storage electrode 7 is formed by alternately depositing a plurality of polysilicon layers and a plurality of oxide layers on the substrate and etching them, and thereafter the whole substrate is immersed in an oxide etching solution to remove all the oxide layers remaining between the polysilicon layers. Then, dielectric layer 8 and plate electrode 9 are formed. However, in this case, the wing portions 12 and 13 of the storage electrode is susceptible to be broken when the substrate is immersed in the etching solution. Namely, if all the oxide layers between the polysilicon layers are removed, the wing portions 12 and 13 of the storage electrode 7 are suspended without any supporting layers, thus resulting in weakening of the wing portions. This drawback decreases the reliability of the process as well as causes unstable structure of a stacked capacitor formed of multiple polysilicon layers.